Sense amplifiers for reading bit lines and bitbar lines from memory cells are well known. Typically these devices precharge bit and bitbar lines to an intermediate value, for example 2.5 volts in a 5 volt system, then read the differential voltage between the bit and bitbar lines when a word line is turned on to connect the memory cell to the bit and bitbar lines. For example, sense amplifiers are described by Weste, N., Eshraghian, K, "Principles of CMOS VLSI Design--A Systems Perspective", Addison-Wesley, 1985, pp 362-364. Other descriptions appear in Glasser, L. A., Dobberpuhl, D. W., "The Design and Analysis of VLSI Circuits", Addison-Wesley, 1985, pp. 283-291; and in Prince, B., "Semiconductor Memories --A Handbook of Design, Manufacture, and Application", Wiley, 1991, pp. 164-165, pp 172-174, pp 255-259, pp. 281-285, and pp 418-420.
In a programmable device which uses the voltage from a memory cell to control a pass transistor, it is important that the act of reading the value in the memory cell not disturb the voltage which controls the pass transistor. Conventional sense amplifiers allow too great a disturbance in the memory cell voltages to be of any value.
Thus it is desirable to provide a sense amplifier which can read a memory cell value without significantly disturbing the memory cell.
In a textbook "Analogue IC Design: The Current Mode Approach" published in 1990 by Peter Peregrinus Ltd. (London) ISBN 086341 2157, at Chapter 12, pages 451-489, author E. Seevinck discusses "Analog Interface Circuits for VLSI". A circuit presented by Seevinck is shown here in FIG. 1. This circuit uses a preamplifier 10 to read a current differential between bit line B and bitbar line B. The current differential is converted to a voltage logic level in a second stage 11. Preamplifier 10 comprises four equally sized PMOS transistors in a cross-coupled configuration. Preamplifier 10 is selected by grounding the select line SEL. Current then flows through bitline loads L1 and L2. The drains of transistors M13 and M14 are connected to data lines D and D, which are pulled close to ground level by transistors T11 and T12. Thus transistors M13 and M14 are fully on.
When memory cell CELL is accessed, current flows either from left to right or from right to left depending upon the value in CELL. The gate/source voltage V.sub.GS of transistor M11 will be equal to that of M13 since their currents are equal and both are in saturation. The same is true of transistors M12 and M14. The differential current between B and B is transferred to D and D, and is amplified and converted to a logic level by second stage 11. Transistors T11 and T12 turn on by different amounts and turn on transistors M51 and M52 by different amounts, in turn producing an amplified voltage difference at node N1 representing D--D, which is then inverted by transistors T13 and T14 to product a signal OUT reflecting the value on bit line B from memory cell CELL.
The circuit of FIG. 1 requires both bit and bitbar signals in order to properly derive a signal OUT which represents the value in CELL. It is sometimes desirable to reliably read a register which holds a user logic value and provides only a single output value connectable to a bit line but no complement connectable to a bitbar line. The circuit of FIG. 1 can not accomplish this goal.
It is further desirable to have a sense amplifier circuit which can latch a value from a memory cell to ease timing constraints on other parts of an integrated circuit of which the memory cell is a part.